XC161 Datasheet, PDF (247/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

21.1.3 CAN Node Control Logic
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.1.3.1 Overview
Each node is equipped with an individual node control logic configuring the global
behavior and providing status information.
The configuration mode is activated when the ACR/BCR register bit CCE is set to ‘1’.
This mode allows modifying the CAN bit timing parameters and the error counter
registers.
The CAN analyzer mode is activated when bit CALM in control register ACR/BCR is set
to ‘1’. In this operation mode, data and remote frames are monitored without an active
participation in any CAN transfer (CAN transmit pin is held on recessive level). Incoming
remote frames are stored in a corresponding transmit message object, while arriving
data frames are saved in a matching receive message object.
In CAN analyzer mode, the entire configuration information of the received frame is
stored in the corresponding message object and can be evaluated by the CPU
concerning their identifier, XTD bit information and data length code. If the remote
monitoring mode is active by RMM = ‘1’, this information is also available for received
remote frames. Incoming frames are not acknowledged and no error frames are
generated. Neither remote frames are answered by the corresponding data frame nor
data frames can be transmitted by setting TXRQ, if CAN analyzer mode is enabled.
Receive interrupts are generated (if enabled) for all correctly received frames and the
respective remote pending RMTPNDn is set in case of received remote frames.
The node specific interrupt configuration is also defined by the node control logic via the
ACR/BCR register bits SIE, EIE and LECIE:
• If control bit SIE is set to ‘1’, a status change interrupt occurs when the ASR/BSR
register has been updated (by each successfully completed message transfer).
• If control bit EIE is set to ‘1’, an error interrupt is generated when a bus-off condition
has been recognized or the error warning level has been exceeded or underrun.
• If control bit LECIE is set to ‘1’, a last error code interrupt is generated when an error
code is set in bitfield LEC in the status registers ASR or BSR.
The status register (ASR/BSR) provides an overview about the current state of the
respective TwinCAN node:
• Flag TXOK is set when a message has been transmitted successfully and
acknowledged by at least one other CAN node,
• flag RXOK indicates an error-free reception of a CAN bus message,
• bitfield LEC indicates the last error occurred on the CAN bus. Stuff, form, and CRC
errors as well as bus arbitration errors (Bit0, Bit1) are reported,
• bit EWRN is set when at least one of the error counters in the error handling logic has
reached the error warning limit (default value 96),
User’s Manual
TwinCAN_X1, V2.1
21-7
V2.2, 2004-01