XC161 Datasheet, PDF (292/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
Field
EWRN
BOFF
0
Bits
6
7
5,
[15:8]
Type
rh
rh
r
Description
Error Warning Status
0 No warning limit exceeded.
1 One of the error counters in the Error
Management Logic reached the error warning
limit of 96.
Bus-Off Status
0 CAN controller is not in the bus-off state.
1 CAN controller is in the bus-off state.
Reserved; returns ‘0’ if read; should be written with ‘0’.
Table 21-7
LEC Error
No Error
Stuff Error
Form Error
Ack Error
Bit1 Error
Bit0 Error
CRC Error
Meaning of the LEC Bitfield
Description
The latest transfer on the CAN bus has been completed successfully.
More than 5 equal bits in a sequence have occurred in a part of a
received message where this is not allowed.
A fixed format part of a received frame has the wrong format.
The transmitted message was not acknowledged by another node.
During a message transmission, the CAN node tried to send a
recessive level (‘1’), but the monitored bus value was dominant
(outside the arbitration field and the acknowledge slot).
Two different conditions are signaled by this code:
1. During transmission of a message (or acknowledge bit, active
error flag, overload flag), the CAN node tried to send a dominant
level (‘0’), but the monitored bus value has been recessive.
2. During bus-off recovery, this code is set each time a sequence of
11 recessive bits has been monitored. The CPU may use this
code as an indication, that the bus is not continuously disturbed.
The CRC checksum of the received message was incorrect.
User’s Manual
TwinCAN_X1, V2.1
21-52
V2.2, 2004-01