XC161 Datasheet, PDF (56/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
Timer T5 in Gated Timer Mode
Gated timer mode for the auxiliary timer T5 is selected by setting bitfield T5M in register
T5CON to 010_B or 011_B. Bit T5M.0 (T5CON.3) selects the active level of the gate input.
Note: A transition of the gate signal at line T5IN does not cause an interrupt request.
f_GPT
T5IN
Prescaler
BPS2 T5I
Gate ^fT5
Ctrl.
T5R ^{0 MUX}
T6R ¹
T5RC
Count
Auxiliary
Timer T5
Clear
T5UD ^Up/Down
T5IRQ
MCB05407
Figure 14-26 Block Diagram of Auxiliary Timer T5 in Gated Timer Mode
Note: There is no output toggle latch for T5.
Start/stop of the auxiliary timer can be controlled locally or remotely.
Timer T5 in Counter Mode
Counter mode for auxiliary timer T5 is selected by setting bitfield T5M in register T5CON
to 001_B. In counter mode, the auxiliary timer can be clocked either by a transition at its
external input line T5IN, or by a transition of timer T6’s toggle latch T6OTL. The event
causing an increment or decrement of a timer can be a positive, a negative, or both a
positive and a negative transition at either the respective input pin or at the toggle latch.
Bitfield T5I in control register T5CON selects the triggering transition (see Table 14-12).
User’s Manual
GPT_X1, V2.0
14-42
V2.2, 2004-01