XC161 Datasheet, PDF (362/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Register TRANSSTAT contains transmission-related status flags and monitors three
functional bits of the header of the currently received frame.
TRANSSTAT
Transmission Status Register
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
Y
K
H
ARL
BR
EAK
HEA
DER
MSG MSG
REC TRA
r
rh rh rh rh rh rh rh rh
Field
MSGTRA
MSGREC
HEADER
BREAK
Bits Type Description
0
rh Message Transmitted
Normal Mode: MSGTRA indicates the complete
transmission of the TxBuffer or IFRVAL (arbitration
won and EOD detected). Reset by bit TxRST.
Block Mode: MSGTRA is set upon a pointer match
after transmission of a byte or ENDF detection. It is
reset when the CPU writes to the transmit buffer or
by bit TXRST.
1
rh Message Received
Normal Mode: MSGREC indicates the reception of
a new frame in the receive buffer on bus side
(detection of ENDF). It is reset by bit RxRST or by
hardware if the buffer is overwritten.
Block Mode: MSGREC is set if the pointers do not
match after reception of a byte (FIFO not empty) or
ENDF detection. It is reset when the CPU reads from
the receive buffer or by bit RXRST.
2
rh Header Received
HEADER is set by hardware after reception of the
complete header byte(s). It is reset by hardware after
reception of the complete frame.
3
rh Break Received
If BREAK is set, a break symbol has been received
on the J1850 bus. Has to be reset by software.
User’s Manual
SDLM_X, V2.0
22-31
V2.2, 2004-01