XC161 Datasheet, PDF (349/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Transmission of a Standard Message in Random Mode
Start
TIP=1 ?
y
n
TxRQ:=0
The transmit buffer should not be
modified while the module is
transmitting.
The transmission request (if
there is still one pending) for
the current transmit buffer is
cleared.
more bytes ?
y
n
TxCPU:=n
ARLRST:=1
TxRST:=1
TxRQ:=1
write byte to
dedicated
address
TxDn
Data bytes (max. 11)
have to be written to the
dedicated addresses
inside the transmit buffer.
In normal mode, TxCPU
is not incremented.
The register TxCPU has to
be set by SW to the
number of bytes which
shall be transmitted
(1 to 11) to be valid for
transmission.
The transmission related
status flags are cleared to get
defined starting conditions.
Other flags can be cleared
optionally.
The transmit buffer is declared
valid (transmission is requested).
TxRQ is automatically reset after
succesful transmission (an
interrupt can be generated, see
bit MSGTRA).
end
Figure 22-12 Transmission in Random Mode
User’s Manual
SDLM_X, V2.0
22-18
V2.2, 2004-01