XC161 Datasheet, PDF (211/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
High-Speed Synchronous Serial Interface (SSC)
19.2.3 Half-Duplex Operation
In a Half-Duplex configuration, only one data line is necessary for both, receiving and
transmitting of data. The data exchange line is connected to both, the MTSR and MRST
pins of each device, the shift clock line is connected to the SCLK pin.
The master device controls the data transfer by generating the shift clock, while the slave
devices receive it. Due to the fact that all transmit and receive pins are connected to the
one data exchange line, serial data may be moved between arbitrary stations.
Similar to Full-Duplex mode, there are two ways to avoid collisions on the data exchange
line:
• only the transmitting device may enable its transmit pin driver
• the non-transmitting devices use open-drain outputs and send only ones (1s).
Because the data inputs and outputs are connected together, a transmitting device will
clock in its own data at the input pin (MRST for a master device, MTSR for a slave). By
this method, any corruptions on the common data exchange line are detected if the
received data is not equal to the transmitted data.
Master
Shift Register
Device #1
MTSR
Transmit
Device #2
MTSR
Slave
Shift Register
MRST
MRST
Clock
SCLK
Clock
SCLK
Clock
Symbols
Input
Push/Pull Output
Open-Drain Output
Tri-Stated = Input
Figure 19-5 SSC Half-Duplex Configuration
User’s Manual
SSC_X, V2.0
19-11
Device #3
MTSR
MRST
SCLK
Slave
Shift Register
Clock
MCA05458
V2.2, 2004-01