XC161 Datasheet, PDF (223/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
20.2
Register Description
In the following, the registers of the IIC-Bus Module are described in detail.
IIC_CON
Control Register
15 14 13 12
----
----
XSFR (E602_H/--)
Reset Value: 0000_H
11 10 9 8 7 6 5 4 3 2 1 0
CI
STP
IGE
TRX
INT
ACK
DIS
BUM
MOD
RSC M10
rw
rwh rw rwh rw rwh rwh
rw
rwh rw
Field
CI
STP
IGE
TRX
INT
Bits Type
[11:10] rw
9
rwh
8
rw
7
rwh
6
rw
Description
Transmit Buffer Length Control
00 1 byte (RTB0)
01 2 bytes (RTB1 … RTB0)
10 3 bytes (RTB2 … RTB0)
11 4 bytes (RTB3 … RTB0)
Master Stop Control
0 No action
1 Setting bit STP generates a stop condition
after the next transmission. Bit BUM is cleared.
Note: STP is automatically cleared by a stop
condition.
Ignore End-of-Transmission (IRQE) Interrupt
0 The IIC is stopped at IRQE interrupt
1 The IIC ignores the IRQE interrupt
Transmit Select
0 No data is transmitted to the IIC bus
1 Data is transmitted to the IIC bus
Note: TRX is set automatically when writing to the
transmit buffer. TRX is automatically cleared
after the last byte as a slave transmitter.
Interrupt Flag Clear Control
0 Interrupt flag IRQD is cleared
by a read/write access to RTB0 … 3
1 Interrupt flag IRQD is not cleared
by a read/write access to RTB0 … 3
User’s Manual
IIC_X, V2.0
20-5
V2.2, 2004-01