XC161 Datasheet, PDF (209/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
High-Speed Synchronous Serial Interface (SSC)
Master
Shift Register
Device #1
MTSR
Transmit
Device #2
MTSR
Slave
Shift Register
MRST
Receive
MRST
Clock
SCLK
Clock
SCLK
Clock
Symbols
Input
Push/Pull Output
Open-Drain Output
Tri-Stated = Input
Device #3
MTSR
Slave
Shift Register
MRST
SCLK
Clock
MCA05457
Figure 19-4 SSC Full-Duplex Configuration
The data output pins MRST of all slave devices are connected together onto the one
receive line in the configuration shown in Figure 19-4. During a transfer, each slave
shifts out data from its shift register. There are two ways to avoid collisions on the receive
line due to different slave data:
• Only one slave drives the line, i.e. enables the driver of its MRST pin. All the other
slaves must have their MRST pins programmed as input so only one slave can put
its data onto the master’s receive line. Only receiving data from the master is
possible. The master selects the slave device from which it expects data either by
separate select lines, or by sending a special command to this slave. The selected
slave then switches its MRST line to output until it gets a de-selection signal or
command.
In the configuration depicted in Figure 19-4, Device #2 is the slave which has its
output driver enabled as push/pull output. Device #3 is an inactive slave, it needs to
disable its output driver by programming the pin to input mode.
• The slaves use their MRST outputs in open-drain mode. This forms a wired-AND
connection. The receive line needs an external pull-up in this case. Corruption of the
User’s Manual
SSC_X, V2.0
19-9
V2.2, 2004-01