XC161 Datasheet, PDF (118/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
17.5
Compare Mode Operation
The compare modes allow triggering of events (interrupts and/or output signal
transitions) or generation of pulse trains with minimum software overhead. In all compare
modes, the 16-bit value stored in a capture/compare register CCy (in the following also
referred to as ‘compare value’) is continuously compared with the contents of the
allocated timer (T0/T7 or T1/T8). If the current timer contents match the compare value,
the interrupt request line associated with register CCy is activated and, depending on the
compare mode, an output signal can be generated at the corresponding output pin
CCyIO.
Four different compare modes are available, which can be selected individually for each
of the capture/compare registers by bitfield MODy in the respective mode control
register. Modes 0 and 2 do not influence the output signals. In the following, each mode
is described in detail.
In addition to these ‘single-register’ modes, a ‘double-register’ compare mode enables
two registers to operate on the same pin. This feature can further reduce software
overhead, as two different compare values can be programmed to control a sequence of
transitions for a signal. See Section 17.5.5 for details for this operation.
In all Compare Modes, the comparator performs an ‘equal to’ comparison. This means,
a match is only detected when the timer contents are equal to the contents of a compare
register. In addition, the comparator is only enabled in the clock cycle directly after the
timer was incremented by hardware. This is done to prevent repeated matches if the
timer does not operate with the highest possible input clock (either in timer or counter
mode). In this case, the timer contents would remain at the same value for several or up
to thousands of cycles. This operation has the side-effect, that software modifications of
the timer contents will have no effect regarding the comparator. If a timer is set by
software to the same value stored in one of the compare registers, no match will be
detected. If a compare register is set to a value smaller than the current timer contents,
no action will take place.
For the exact operation of the port output function, please see Section 17.6.
When two or more compare registers are programmed to the same compare value¹⁾,
their corresponding interrupt request flags will be set and the selected output signals will
be generated after the allocated timer is incremented to this compare value. Further
compare events on the same compare value are disabled²⁾ until the timer is incremented
again or written to by software. After a reset, compare events for register CCy will only
become enabled, if the allocated timer has been incremented or written to by software
and one of the compare modes described in the following has been selected for this
register.
1) In staggered mode these interrupts and output signals are generated sequentially (see Section 17.8).
2) Even if more compare cycles are executed before the timer increments (lower timer frequency) a given
compare value only results in one single compare event.
User’s Manual
CC12_X1, V2.1
17-14
V2.2, 2004-01