XC161 Datasheet, PDF (355/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.3.1 Global Control and Timing Registers
The Global Control Register contains bits to select different transfer modes and to
determine the message handling.
GLOBCON
Global Control Register
15 14 13 12 11 10 9
0
r
Reset Value: 0000_H
876543210
PB AR
SEL IFR
OV
WR
NB
HDT
BM
EN
EN
4x
GM
EN
rw rw rw rw rw rw rw rw
Field
GMEN
EN4X¹⁾
BMEN
HDT
NB
Bits Type Description
0
rw Global Module Enable
0 The complete SDLM module is disabled.
1 The SDLM module is enabled and data
transmission via the serial bus is possible.
Resetting GMEN by software from ‘1’ to ‘0’ resets the
module, except the timings.
1
rw High Speed Transfer Enable (4x)
0 The data transfer rate is 10.4 kbit/s.
1 The data transfer rate is 41.6 kbit/s.
2
rw Block Mode Enable
0 The maximum frame length is 11 data bytes
(normal mode).
1 Transfers of frames longer than 11 data bytes
are enabled.
The transmit and the receive buffers are organized
as circular buffers, which can be accessed in FIFO
mode. Resetting BMEN resets the buffer pointers.
3
rw Header Type
0 Single byte headers are supported.
1 Consolidated headers (1 byte and 3 bytes) are
supported.
4
rw Normalization Bit Polarity
0 Normalization bit is functional 0.
1 Normalization bit is functional 1.
User’s Manual
SDLM_X, V2.0
22-24
V2.2, 2004-01