XC161 Datasheet, PDF (361/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

Field
RBB
RBC
0
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Bits Type Description
3
rh Receive Buffer on Bus Side Full
RBB = ‘1’ indicates that the receive buffer on J1850
side is full. In case of a new incoming message, this
buffer is declared empty (RBB = 0) and overwritten
by the new data if bit OVWR = ‘1’. If bit OVWR = 0,
the buffer status and its contents are not changed
(new data is not received). RBB is reset by hardware
when the buffer is swapped to CPU side.
In block mode, (only one buffer, so RBB = RBC) RBB
is set upon a pointer match after reception of a byte.
It is reset by reading from the receive buffer.
4
rh Receive Buffer on CPU Side Full
RBC = ‘1’ indicates that the receive buffer on CPU
side is full (not empty). This buffer remains allocated
by the CPU and bit RBC remains set until bit DONE
has been set by software.
[15:5] –
Reserved; returns ‘0’ if read.
User’s Manual
SDLM_X, V2.0
22-30
V2.2, 2004-01