XC161 Datasheet, PDF (175/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
Non-Standard Baudrates
Due to the relationship between Br0 to Br8 in Table 18-8 concerning the divide factor d_f
other baudrates than the standard baudrates can be also selected. E.g. if a baudrate of
50 kbit/s has to be detected, Br2 is e.g. defined as baudrate for the 50 kbit/s selection.
This further results in:
f_DIV = 50 kbit/s × d_f@Br2 = 50 kbit/s × 192 = 9.6 MHz
Therefore, depending on the module clock frequency f_ASC, the value of the fractional
divider (register FDV must be set in this example according to the formula:
FDV = ^{5----1---2-----×}-----^f--^D---^I--^V-
f_ASC
with f_DIV = 9.6 MHz
(18.3)
Using this selection (f_DIV = 9.6 MHz), the detectable baudrates start at 200 kbit/s (Br0)
down to 1042 bit/s (Br8). Table 18-10 shows the baudrate table for this example.
Table 18-10 Autobaud Detection Using Non-Standard Baudrates (f_DIV = 9.6 MHz)
Baudrate Detectable Non-
Divide Factor d_f BG is Loaded after
Numbering Standard Baudrates
Detection with Value
Br0
200.000 kbit/s
48
Br1
100.000 kbit/s
96
Br2
50 kbit/s
192
Br3
33.333 kbit/s
288
Br4
16.667 kbit/s
576
Br5
8333 bit/s
1152
Br6
4167 bit/s
2304
Br7
2083 bit/s
4608
Br8
1047 bit/s
9216
2 = 002_H
5 = 005_H
11 = 00B_H
17 = 011_H
35 = 023_H
71 = 047_H
143 = 08F_H
287 = 11F_H
575 = 23F_H
User’s Manual
ASC_X, V2.0
18-32
V2.2, 2004-01