XC161 Datasheet, PDF (224/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

Field
ACKDIS
BUM
MOD
RSC
M10
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
Bits Type Description
5
rwh Acknowledge Pulse Disable
0 An acknowledge pulse is generated for each
received byte
1 No acknowledge pulse is generated
Note: ACKDIS is automatically cleared by a stop
condition.
4
rwh Busy Master
0 Clearing bit BUM immediately generates a
stop condition
1 Setting bit BUM generates a start condition in
(multi-) Master mode
Note: Setting bit BUM while the bus is busy (BB = 1)
generates an arbitration lost situation.
In this case, BUM is cleared and bit AL is set.
BUM cannot be set in slave mode.
[3:2] rw
Basic Operating Mode
00 IIC module is disabled and initialized (Init-
Mode). Transmissions in progress will be
aborted.
01 Slave mode
10 Single-Master mode
11 Multi-Master mode
1
rwh Repeated Start Condition Trigger
0 No operation
1 Generate a repeated start condition in (multi-)
master mode. RSC cannot be set in slave
mode.
Note: RSC is cleared automatically after the
repeated start condition has been sent.
0
rw
Slave Address Width Selection
0 7-bit slave address, using ICA[7:1]
1 10-bit slave address, using ICA[9:0]
User’s Manual
IIC_X, V2.0
20-6
V2.2, 2004-01