XC161 Datasheet, PDF (297/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
Field
TSEG2
DIV8X
LBM
0
Bits
[14:12]
Low
15
Low
0
High
[15:1]
High
Type Description
rw Time Segment After Sample Point
(TSEG2+1) time quanta after the sample point take
into account a user defined delay and compensate a
mismatch between transmitter and receiver clock
phase.
Valid values for TSEG2 are 1 … 7.
rw Division of Module Clock f_CAN by 8
0 The baudrate prescaler is directly driven by f_CAN.
1 The baudrate prescaler is driven by f_CAN/8.
rw Loop-Back Mode
0 Loop-back mode is disabled.
1 Loop-back mode is enabled, if bits LBM are set
in the BTR registers of Node A and Node B.
r
Reserved; read as ‘0’; should be written with ‘0’.
Note: Modifying the contents of register ABTR/BBTR requires bit CCE = ‘1’ in register
ACR/BCR.
User’s Manual
TwinCAN_X1, V2.1
21-57
V2.2, 2004-01