XC161 Datasheet, PDF (214/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
High-Speed Synchronous Serial Interface (SSC)
19.2.6 Error Detection Mechanisms
The SSC is able to detect four different error conditions. Receive Error and Phase Error
are detected in all modes; Transmit Error and Baudrate Error only apply to Slave Mode.
When an error is detected, the respective error flag in register SSCx_CON is set and an
error interrupt request will be generated by activating the EIRQ line (see Figure 19-7).
The error interrupt handler may then check the error flags to determine the cause of the
error interrupt. The error flags are not reset automatically but rather must be cleared by
software after servicing. This allows servicing of some error conditions via interrupt,
while the others may be polled by software.
Note: The error interrupt handler must clear the associated (enabled) error flag(s) to
prevent repeated interrupt requests.
Bits in Register
CON
TEN
&
Transmit
Error
TE
REN
&
Receive
Error
RE
PEN
&
Phase
Error
PE
BEN
&
Baudrate
Error
BE
>^_1
Error Interrupt
Request EIRQ
MCA05460
Figure 19-7 SSC Error Interrupt Control
A Receive Error (Master or Slave Mode) is detected when a new data frame is
completely received but the previous data was not read out of the receive buffer register
SSCx_RB. This condition sets the error flag RE and, when enabled via bit REN, the error
interrupt request line EIRQ. The old data in the receive buffer SSCx_RB will be
overwritten with the new value and is irretrievably lost.
A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST
(Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module
User’s Manual
SSC_X, V2.0
19-14
V2.2, 2004-01