XC161 Datasheet, PDF (149/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

18.2.1
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
Asynchronous Data Frames
8-Bit Data Frames
8-bit data frames consist of either eight data bits D7 … D0 (M = 001_B), or seven data bits
D6 … D0 plus an automatically generated parity bit (M = 011_B). Parity may be odd or
even, depending on bit ODD. An even parity bit will be set if the modulo-2-sum of the
7 data bits is 1. An odd parity bit will be cleared in this case. Parity checking is enabled
via bit PEN (always OFF in 8-bit data mode). The parity error flag PE will be set, along
with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself
will be stored in bit RBUF.7.
M = 001_B
10-/11-bit UART Frame
8 Data Bits
11
Start
Bit
0
D0
LSB
D1
D2
D3
D4
D5
D6
D7
MSB
(1^st)
Stop
Bit
(2^nd)
Stop
Bit
M = 011_B
10-/11-bit UART Frame
7 Data Bits
11
Start
Bit
0
D0
LSB
D1
D2
D3
D4
D5
D6
MSB
Parity
Bit
(1^st)
Stop
Bit
(2^nd)
Stop
Bit
MCT05435
Figure 18-4 Asynchronous 8-Bit Frames
User’s Manual
ASC_X, V2.0
18-6
V2.2, 2004-01