XC161 Datasheet, PDF (152/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
18.2.2 Asynchronous Transmission
Asynchronous transmission begins at the next overflow of the divide-by-16 baudrate
timer (transition of the baudrate clock f_BR), if bit R is set and data has been loaded into
TBUF. The transmitted data frame consists of three basic elements:
• Start bit
• Data field (eight or nine bits, LSB first, including a parity bit, if selected)
• Delimiter (one or two stop bits)
Data transmission is double-buffered. When the transmitter is idle, the transmit data
loaded in the transmit buffer register is immediately moved to the transmit shift register,
thus freeing the transmit buffer for the next data to be sent. This is indicated by the
transmit buffer interrupt request line TBIR being activated. TBUF may now be loaded
with the next data, while transmission of the previous data continues.
The transmit interrupt request line TIR will be activated before the last bit of a frame is
transmitted, that is, before the first or the second stop bit is shifted out of the transmit
shift register.
Note: The transmitter output pin TxD must be configured for alternate data output.
18.2.3 Transmit FIFO Operation
The transmit FIFO (TXFIFO) provides the following functionality:
• Enable/disable control
• Programmable filling level for transmit interrupt generation
• Filling level indication
• FIFO clear (flush) operation
• FIFO overflow error generation
The 8-stage transmit FIFO is controlled by the TXFCON control register. When bit
TXFEN is set, the transmit FIFO is enabled. The interrupt trigger level defined by TXFITL
defines the filling level of the TXFIFO at which a transmit buffer interrupt TBIR or a
transmit interrupt TIR is generated. These interrupts are always generated when the
filling level of the transmit FIFO is equal to or less than the value stored in TXFITL.
Bitfield TXFFL in the FIFO status register ASCx_FSTAT indicates the number of entries
that are actually written (valid) in the TXFIFO. Therefore, the software can verify, in the
interrupt service routine, for instance, how many bytes can still be written into the
transmit FIFO via register TBUF without getting an overrun error.
The transmit FIFO cannot be accessed directly. All data write operations into the TXFIFO
are executed by writing into the TBUF register.
User’s Manual
ASC_X, V2.0
18-9
V2.2, 2004-01