XC161 Datasheet, PDF (126/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
Case 5 shows an option to get around this problem. Here, the compare register is
reloaded with FFF8_H, a value which is lower than the timer reload value. Thus, the timer
will never reach this value, and no compare match will be detected. The output signal will
be set to 0 after the first timer overflow. However, after the second overflow, software
now reloads the compare register with a regular compare value. As no compare blocking
has taken place (since there was no compare match), the newly written compare value
will go into effect during the current timer period.
17.5.5 Double-Register Compare Mode
The Double-Register Compare Mode makes it possible to further reduce software
overhead for a number of applications. In this mode, two compare registers work
together to control one output. This mode is selected via the DRM register, or by a
special combination of compare modes for the two registers.
For double-register compare mode, the 16 capture/compare registers of a CAPCOM unit
are regarded as two banks of 8 registers each. The lower eight registers form bank1,
while the upper eight registers form bank2. For double-register mode, a bank1 register
and a bank2 register form a register pair. Both registers of this register pair operate on
the pin associated with the bank1 register.
The relationship between the bank1 and bank2 register of a pair and the effected output
pins for double-register compare mode is listed in Table 17-3.
Table 17-3 Register Pairs for Double-Register Compare Mode
CAPCOM1 Unit
CAPCOM2 Unit
Register Pair Used
Bank 1 Bank 2 ^Output
Pin
Control
Register Pair Used
Bitfield in _{Bank 1 Bank 2} Output
CC1DRM
Pin
Control
Bitfield in
CC2DRM
CC0
CC8 CC0IO DR0M
CC16 CC24 CC16IO DR0M
CC1
CC9 CC1IO DR1M
CC17 CC25 CC17IO DR1M
CC2
CC10 CC2IO DR2M
CC18 CC26 CC18IO DR2M
CC3
CC11 CC3IO DR3M
CC19 CC27 CC19IO DR3M
CC4
CC12 CC4IO DR4M
CC20 CC28 CC20IO DR4M
CC5
CC13 CC5IO DR5M
CC21 CC29 CC21IO DR5M
CC6
CC14 CC6IO DR6M
CC22 CC30 CC22IO DR6M
CC7
CC15 CC7IO DR7M
CC23 CC31 CC23IO DR7M
The double-register compare mode can be programmed individually for each register
pair. Double-register compare mode can be selected via a certain combination of
compare modes for the two registers of a pair. The bank1 register must be programmed
User’s Manual
CC12_X1, V2.1
17-22
V2.2, 2004-01