XC161 Datasheet, PDF (356/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Field
Bits Type Description
OVWR
5
rw Overwrite Enable
0 Overwrite action of the receive buffer on SDLM
side in case of an incoming frame and a full
receive buffer on bus side (RBB = 1) disabled.
The frame on the bus is not accepted and is
lost.
1 The full buffer on bus side is declared empty
and then overwritten by the next incoming
frame. The frame in the receive buffer on bus
side is lost.
ARIFR
6
rw Automatic Retry of IFR
0 The module will not retry transmission of IFR
byte(s) in case of an arbitration loss (handling
of IFR types 1, 3). The collision detection
mechanism is generally enabled during IFR.
1 An automatic retry of IFR transmission in case
of arbitration loss is enabled (for IFR type 2).
The collision detection mechanism is disabled
during EOD.
PBSEL
7
rw Passive Bits Select
0 When loosing arbitration during the last bit of a
byte (on a byte boundary) during the normal
frame, two passive bits are automatically
transmitted by the module. The passive bits
are never added during IFR.
1 No extra action after the loss of arbitration (the
two passive bits are not added).
0
[15:8] –
Reserved; returns ‘0’ if read; should be written with
‘0’.
1) In order to support transmission in 4x mode, the transceiver delay should not exceed 4 µs.
User’s Manual
SDLM_X, V2.0
22-25
V2.2, 2004-01