XC161 Datasheet, PDF (106/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
With this mechanism, each CAPCOM unit supports generation and control of timing
sequences on up to 16 channels with a minimum of software intervention.
From the programmer’s point of view, the term ‘CAPCOM unit’ refers to a set of registers
which are associated with this peripheral, including the port pins which may be used for
alternate input/output functions, and their direction control bits (see also Figure 17-1).
A CAPCOM unit is typically used to handle high speed IO tasks such as pulse and
waveform generation, pulse width modulation, or recording of the time when a specific
event occurs. It also supports the implementation of up to 16 software-controlled
interrupt events.
Each CAPCOM Unit consists of two 16-bit timers (T0/T1, T7/T8), each with its own
reload register (TxREL), and a bank of sixteen dual-purpose 16-bit capture/compare
registers (CCy).
The input clock for the CAPCOM timers is programmable to several prescaled values of
the module input clock (f_CC), or it can be derived from the overflow/underflow of timer T6.
T0/T7 may also operate in counter mode (from an external input), clocked by external
events.
Each capture/compare register may be programmed individually for capture or compare
operation, and each register may be allocated to either of the two timers. Each
capture/compare register has one signal associated with it, which serves as an input
signal for the capture operation or as an output signal for the compare operation.
The capture operation causes the current timer contents to be latched into the respective
capture/compare register, triggered by an event (transition) on the associated input
signal. This event also activates the associated interrupt request line.
The compare operation may cause an output signal transition on the associated output
signal, when the allocated timer increments to the value stored in a capture/compare
register. The compare match event also activates the associated interrupt request line.
In Double-register compare mode a pair of registers controls one common output signal.
The compare output signals are available via a dedicated output register, and may also
control the output latches of the connected port pins. The output path can be selected.
For the switching of the output signals two timing schemes (see Section 17.8) can be
selected:
In Staggered Mode¹⁾ the output signals are switched consecutively in 8 steps, which
distributes the switching steps over a certain time. In staggered mode, the maximum
resolution is 8 t_CC.
In Non-Staggered Mode the output signals are switched immediately at the same time.
In non-staggered mode, the maximum resolution is 1 t_CC.
Figure 17-2 shows the basic structure of a CAPCOM unit.
1) Staggered mode is compatible with the CAPCOM units of previous 16-bit controllers.
User’s Manual
CC12_X1, V2.1
17-2
V2.2, 2004-01