XC161 Datasheet, PDF (303/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
The Interrupt Mask Registers AIMR4/BIMR4 are used to enable the node specific
interrupt sources (last error, correct reception, error warning/bussoff) for the generation
of the corresponding INTID value.
AIMR4
Node A INTID Mask Register 4
BIMR4
Node B INTID Mask Register 4
Reset Value: 0000_H
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
IMC IMC IMC
34 33 32
r
rw rw rw
Field
IMC32
IMC33
IMC34
0
Bits
0
1
2
[15:3]
Type Description
rw Last Error Interrupt INTID Mask Control
0 The last error interrupt source is ignored for
the generation of the INTID value.
1 The last error interrupt source is taken into
account for the generation of the INTID
value.
rw TX/RX Interrupt INTID Mask Control
0 The TX/RX interrupt source is ignored for the
generation of the INTID value.
1 The TX/RX interrupt pending status is taken
into account for the generation of the INTID
value.
rw Error Interrupt INTID Mask Control
0 The error interrupt source is ignored for the
generation of the INTID value.
1 The error interrupt pending status is taken
into account for the generation of the INTID
value.
r
Reserved; read as ‘0’; should be written with ‘0’.
User’s Manual
TwinCAN_X1, V2.1
21-63
V2.2, 2004-01