XC161 Datasheet, PDF (249/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.1.3.2 Timing Control Unit
According to ISO-DIS 11898 standard, a CAN bit time is subdivided into different
segments (Figure 21-4). Each segment consists of multiples of a time quantum t_q. The
magnitude of t_q is adjusted by the bitfield BRP and by bit DIV8X, both controlling the
baud rate prescaler (see bit timing register ABTR/BBTR). The baud rate prescaler is
driven by the CAN module clock f_CAN.
T_Sync
T_Prop
1 Bit Time
T_Seg1
T_b1
T_Seg2
T_b1
Sync.
Segment
1 Time Quantum (t_q)
Sample Point
Transmit Point
MCT05474
Figure 21-4 CAN Bus Bit Timing Standard
The synchronization segment (T_Sync) allows a phase synchronization between
transmitter and receiver time base. The synchronization segment length is always 1 t_q.
The propagation time segment (T_Prop) takes into account the physical propagation delay
in the transmitter output driver, on the CAN bus line and in the transceiver circuit. For a
working collision detect mechanism, T_Prop has to be two times the sum of all propagation
delay quantities rounded up to a multiple of t_q. The phase buffer segments 1 and 2 (T_b1,
T_b2) before and after the signal sample point are used to compensate a mismatch
between transmitter and receiver clock phase detected in the synchronization segment.
The maximum number of time quanta allowed for resynchronization is defined by bitfield
SJW in bit timing register ABTR/BBTR. The propagation time segment and the phase
buffer segment 1 are combined to parameter T_Seg1, which is defined by the value TSEG1
in the respective bit timing register ABTR/BBTR. A minimum of 3 time quanta is
requested by the ISO standard. Parameter T_Seg2, which is defined by the value of TSEG2
in the bit timing register ABTR/BBTR, covers the phase buffer segment 2. A minimum of
2 time quanta is requested by the ISO standard. According ISO standard, a CAN bit time,
calculated as the sum of T_Sync, T_Seg1 and T_Seg2, must not fall below 8 time quanta.
Note: The access to bit timing register ABTR/BBTR is only enabled if bit CCE in control
register ACR/BCR is set to ‘1’.
User’s Manual
TwinCAN_X1, V2.1
21-9
V2.2, 2004-01