XC161 Datasheet, PDF (296/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
The Bit Timing Register contains all parameters to adjust the data transfer baud rate and
the bit timing.
ABTRH
Node A Bit Timing Register High
ABTRL
Node A Bit Timing Register Low
BBTRH
Node B Bit Timing Register High
BBTRL
Node B Bit Timing Register Low
Reset Value: 0000_H
Reset Value: 0000_H
Reset Value: 0000_H
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
LBM
r
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
8X
TSEG2
rw
rw
TSEG1
rw
SJW
rw
BRP
rw
Field
BRP
SJW
TSEG1
Bits
[5:0]
Low
[7:6]
Low
[11:8]
Low
Type Description
rw Baudrate Prescaler
One bit time quantum corresponds to the period length
of the external oscillator clock multiplied by (BRP+1),
depending also on bit DIV8X.
rw (Re)Synchronization Jump Width
(SJW+1) time quanta are allowed for
resynchronization.
rw Time Segment Before Sample Point
(TSEG1+1) time quanta before the sample point take
into account the signal propagation delay and
compensate a mismatch between transmitter and
receiver clock phase.
Valid values for TSEG1 are 2 … 15.
User’s Manual
TwinCAN_X1, V2.1
21-56
V2.2, 2004-01