XC161 Datasheet, PDF (146/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
18.1
Operational Overview
Figure 18-2 shows a block diagram of the ASC with its operating modes (Asynchronous
and Synchronous Mode).
Asynchronous Mode
f_ASC
Prescaler /
Fractional
f_DIV
Divider
Autobaud
Detection
Baudrate
Timer
Serial Port
Control
RxD
IrDA
Decoding
MUX
Receive / Transmit
Buffers and
Shift Registers
IrDA
Decoding
MUX
TxD
Synchronous Mode
2
f_ASC
or
3
Baudrate
Timer
Serial Port
Control
Shift Clock
TxD
Receive / Transmit
RxD
Buffers and
Shift Registers
RxD
MCB05433
Figure 18-2 Block Diagram of the ASC
The ASC supports full-duplex asynchronous communication with up to 2.5 Mbit/s and
half-duplex synchronous communication with up to 5 Mbit/s (@ 40 MHz module clock).
In Synchronous Mode, data are transmitted or received synchronous to a shift clock that
is generated by the microcontroller. In Asynchronous Mode, either 8- or 9-bit data
transfer, parity generation, and the number of stop bits can be selected. Parity, framing,
and overrun error detection is provided to increase the reliability of data transfers.
Transmission and reception of data is double-buffered. For multiprocessor
communication, a mechanism is provided to distinguish address bytes from data bytes.
User’s Manual
ASC_X, V2.0
18-3
V2.2, 2004-01