XC161 Datasheet, PDF (348/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

22.2.7.2 Transmission Control
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Transmission of a Standard Message in FIFO Mode
Bit TxINCE in register BUFFCON has to be set in order to provide FIFO functionality.
Bitfield TxCPU is incremented after each write operation to TxD0. The transmit buffer is
filled by multiple write actions to TxD0. All other registers of the transmit buffer can
always be directly accessed via their addresses without changing TXCPU.
Start
TIP=1 ?
y
n
TxRQ:=0
The transmit buffer should not be
modified while the module is
transmitting.
The transmission request (if
there is still one pending) for
the current transmit buffer is
cleared.
more bytes ?
y
n
TxCPU >0 ?
n
y
ARLRST:=1
TxRST:=1
TxRQ:=1
write byte to
TxD0
Data bytes (max. 11) are
written to the FIFO base
address. In FIFO mode,
TxCPU is automatically
incremented after each
write to TxD0.
The transmit buffer has to
be filled (at least one byte)
to be valid for transmission.
The transmission related
status flags are cleared to get
defined starting conditions.
Other flags can be cleared
optionally.
The transmit buffer is declared
valid (transmission is requested).
TxRQ is automatically reset after
succesful transmission (an
interrupt can be generated, see
bit MSGTRA).
end
Figure 22-11 Transmission in FIFO Mode
User’s Manual
SDLM_X, V2.0
22-17
V2.2, 2004-01