XC161 Datasheet, PDF (341/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.2.3.1 Message Operating Mode
Basically two receive buffers (11 byte each) and one 11 byte transmit buffer are available
for data transfer. This allows the transfer of a complete J1850 frame without reloading
data bytes. The access to the data is handled in FIFO mode (read/write to one address)
in addition to random mode (read/write to selected bytes at consecutive addresses). In
case of a loss of arbitration, an automatic retransmission is started, until the transmit
request bit (TXRQ) is reset by the CPU. For correct transmission, the transmit buffer has
to contain valid data (TXCPU > 0) when TXRQ is set.
22.2.3.2 Receive Operation
The receive buffer structure contains two independent 11 byte receive buffers. One of
them is located on CPU side and can be directly accessed by the CPU (data and
pointers). If this buffer is full (not yet completely read out), it can not be accessed by the
J1850 module. Data reception over the bus is always done via the receive buffer on bus
side. In order to release the receive buffer on CPU side, bit DONE has to be set. After
complete reception of a frame, the buffer on J1850 side is declared full. If both buffers
are full, the buffer on J1850 side can be overwritten by a new incoming frame, depending
on the user-programmable overwrite enable bit (OVWR). If the CPU buffer is empty and
the J1850 buffer is full, both buffers are swapped. By this action, the full buffer can be
accessed by the CPU and the empty one is available on J1850 side.
The total number of received bytes in the corresponding buffer is indicated by bitfield
RxCNT. Bitfield RxCPU indicates how many bytes have already been read out. In FIFO
mode (RxINCE = 1), CPU data read actions take place via register RxD00 and RxCPU
is automatically incremented by 1 after each read action. In Random Mode
(RxINCE = 0), the buffer bytes can be directly accessed via their address. In this case,
RxCPU is not incremented. In order to release a buffer for new message reception, the
DONE bit has to be set. A receive interrupt is generated after complete reception of the
whole frame (MSGREC = 1).
Register BUFFCON provides flags controlling the receive buffer:
• Receive Buffer Increment Enable (RxINCE): This bit enables FIFO Mode in addition
to random mode: In random mode the CPU has access to each receive buffer byte
via its address. In FIFO mode, the RxCPU pointer is incremented upon CPU read
access until RxCPU == RxCNT (max. 11). This mode allows an easy CPU read
transfer from the receive buffer only by addressing RxD00.
Register BUFFSTAT contains information about the receive buffer:
• RBC, RBB indicate valid data in the receive buffers
• MSGLST indicates a lost frame due to a full receive buffer
• Receive in Progress (RIP) indicates if any receive action is pending
• Break symbol reception is indicated by Break Received bit (BREAK)
User’s Manual
SDLM_X, V2.0
22-10
V2.2, 2004-01