XC161 Datasheet, PDF(123/419 Page) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC161 Datasheet, PDF (123/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

Capture/Compare Units

Timer T0/T7

Timer T1/T8

T1IRQ,

T8IRQ

T0IRQ,

T7IRQ

ACCy

MODy

Mode

Control

Comparator

=?

ACCy

Mode 3 only!

Mode &

Output Ctrl.

to Port

Logic

CCyIRQ

SEEy SEMy

Compare

Register CCy

MCB05423

Figure 17-7 Compare Mode 2 and 3 Block Diagram

Note: The port latch and signal remain unaffected in compare mode 2.

Figure 17-8 illustrates a few timing examples for compare modes 2 and 3.

In all examples, the reload value of the used timer is set to FFF9H. When the timer

overflows, it starts counting from this value upwards.

In Case 1, register CCy contains the value FFFCH. When the timer reaches this value,

a match is detected, and the interrupt request line CCyIRQ is activated. In compare

mode 2, this is all that will happen. In compare mode 3, additionally the associated port

output is set to 1. The timer continues to count, and finally reaches its overflow. At this

point, the port output is reset to 0 again. Note that, although not shown in the diagrams,

the overflow signal of the timer also activates the associated interrupt request line

TxIRQ. If the contents of register CCy are not changed, the port output will be set again

during the following timer period, and reset again when the timer overflows. This

operation is ideal for the generation of a pulse width modulated (PWM) signal with a

minimum of software overhead. The pulse width is varied by changing the compare

value accordingly.

In Case 2, the compare operation is blocked after the first match within a timer period.

After the first match at FFFCH, the interrupt request is generated and the port output is

set. In addition, further compare matches are disabled. If now a new compare value is

written to register CCy, no interrupt request and no port output influence will take place,

although the new compare value is higher than the current timer contents. Only after the

overflow of the timer, the compare logic is enabled again, and the next match will be

Userâs Manual

CC12_X1, V2.1

17-19

V2.2, 2004-01

▷