XC161 Datasheet, PDF (253/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
register ACR/BCR is set to ‘1’, an interrupt request is generated on any modification of
bits EWRN and BOFF. The associated interrupt node pointer is defined by bitfield EINP
in control register AGINP/BGINP.
21.1.3.6 Message Interrupt Processing
Each message object is equipped with 2 interrupt request sources indicating the
successful end of a message transmission or reception.
Correct Transfer of
Message Object n
Transmit
Receive
TXIE TXIPND
TXINP
>^_ 1
INTPND
RXIE RXIPND
RXINP
MCA05476
Figure 21-6 Message Specific Interrupt Control
The message based transfer interrupt sources are enabled, if bit TXIE or RXIE in the
associated message control register MSGCTRn are set to ‘10’. The associated interrupt
node pointers are defined by bitfields RXINP and TXINP in message configuration
register MSGCFGn.
21.1.3.7 Interrupt Indication
The AIR/BIR register provides an INTID bitfield indicating the source of the pending
interrupt request with the highest internal priority (lowest message object number). The
type of the monitored interrupt requests, taken into account by bitfield INTID, can be
selected by registers AIMR0/AIMR4 and BIMR0/BIMR4 containing a mask bit for each
interrupt source. If no interrupt request is pending, all bits of AIR/BIR are cleared. The
interrupt requests INTPNDn have to be cleared by software.
User’s Manual
TwinCAN_X1, V2.1
21-13
V2.2, 2004-01