XC161 Datasheet, PDF (120/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
Timer T0/T7
Timer T1/T8
T1IRQ,
T8IRQ
T0IRQ,
T7IRQ
ACCy
MODy
Mode
Control
Comparator
=?
Mode 1 only!
Mode &
Output Ctrl.
to Port
Logic
CCyIRQ
SEEy SEMy
Compare
Register CCy
MCB05421
Figure 17-5 Compare Mode 0 and 1 Block Diagram
Note: The signal remains unaffected in compare mode 0.
Figure 17-6 illustrates a few example cases for compare modes 0 and 1.
In all examples, the reload value of the used timer is set to FFF9_H. When the timer
overflows, it starts counting from this value upwards.
In Case 1, register CCy contains the value FFFC_H. When the timer reaches this value,
a match is detected, and the interrupt request line CCyIRQ is activated. In compare
mode 0, this is all that will happen. In compare mode 1, additionally the associated port
output is toggled, causing an inversion of the output signal. If the contents of register CCy
are not changed, this operation will take place each time the timer reaches the
programmed compare value.
In Case 2, software reloads the compare register CCy with FFFF_H after the first match
with FFFC_H has occurred. As the timer continues to count up, it finally reaches this new
compare value, and a new match is detected, activating the interrupt request line (both
modes) and toggling the output signal (compare mode 1). If then the compare value is
left unchanged, the next match will occur when the timer reaches FFFF_H again.
This example illustrates, that further compare matches are possible within the current
timer period (this is in contrast to compare modes 2 and 3).
User’s Manual
CC12_X1, V2.1
17-16
V2.2, 2004-01