XC161 Datasheet, PDF (375/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Register RXCPU contains the number of bytes already read out from this buffer.
RXCPU
CPU Receive Byte Counter Register (on CPU side)
15 14 13 12 11 10 9 8 7 6 5
0
r
Reset Value: 0000_H
43210
RxCPU
rwh
Field
RxCPU
0
Bits Type Description
[3:0] rwh CPU Receive Byte Counter
Bitfield RxCPU contains the number of bytes read
out by the CPU. In FIFO mode (RxINCE = ‘1’ or
BMEN = ‘1’), RXCPU is incremented by 1 after each
CPU read action to register RxD00.
In random mode (RxINCE = 0 and BMEN = 0),
RxCPU is not used and is 0.
= pointer for CPU access to receive buffer
RxCPU is reset when the receive buffer on CPU side
is released.
[15:4] –
Reserved; returns ‘0’ if read; should be written with
‘0’.
User’s Manual
SDLM_X, V2.0
22-44
V2.2, 2004-01