XC161 Datasheet, PDF (366/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Register BUFFCON contains the transfer-related control bits, including IFR control and
FIFO control.
BUFFCON
Buffer Control Register
15 14 13 12 11 10 9
0
r
Reset Value: 0000_H
876543210
RX TX IFR CRC S DO TX TX
INCE INCE EN EN BRK NE RQ IFR
rw rw rw rw rwh rwh rwh rwh
Field
TXIFR
TXRQ
DONE
SBRK
Bits Type Description
0
rwh Transmit In-Frame Response
Setting bit TXIFR declares the transmit buffer or the
IFR register (if IFREN = 1, IFR type 1, 2, others than
3 byte consolidated header) to be valid for IFR and
initiates its transmission. TXIFR is automatically
reset by hardware after successful transmission.
Resetting TxIFR by software stops the transmission
of the IFR.
1
rwh Transmit Request
Setting bit TXRQ declares the transmit buffer to be
valid and starts its transmission. TXRQ is
automatically reset by hardware after successful
transmission. Resetting TxRQ by software stops the
transmission in Normal Mode and in Block Mode.
TXRQ can not be used to start IFR transmission from
the transmit buffer.
If TXRQ is reset, TXCPU is cleared.
2
rwh Receive Buffer on CPU Side Read Out Done
Setting bit DONE declares the receive buffer on CPU
side to be empty, resets RXCPU and releases the
buffer (reset of RBC). If there is a full receive buffer
on bus side, the buffers are swapped. This bit is reset
by hardware after the buffer has been released.
3
rwh Send Break
Setting bit SBRK initiates the transmission of a break
symbol on the J1850 bus. Bit SBRK is reset by
hardware after having sent the break symbol.
User’s Manual
SDLM_X, V2.0
22-35
V2.2, 2004-01