XC161 Datasheet, PDF (119/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
17.5.1 Compare Mode 0
This is an interrupt-only mode which can be used for software timing purposes. In this
mode, the interrupt request line CCyIRQ is activated each time a match is detected
between the contents of the compare register CCy and the allocated timer. A match
means, the contents of the timer are equal to (‘=’) the contents of the compare register.
Several of these compare events are possible within a single timer period, if the compare
value in register CCy is updated during the timer period. The corresponding port signal
CCyIO is not affected by compare events in this mode and can be used as general
purpose IO.
Note: If compare mode 0 is programmed for one of the bank2 registers the double-
register compare mode may be enabled for this register (see Chapter 17.5.5).
17.5.2 Compare Mode 1
This is a compare mode which influences the associated output signal. Besides this, the
basic operation is as in compare mode 0. Each time a match is detected between the
contents of the compare register CCy and the allocated timer, the interrupt request line
CCyIRQ is activated. In addition, the associated output signal is toggled. Several of
these compare events are possible within a single timer period, if the compare value in
register CCy is updated during the timer period.
Note: If compare mode 1 is programmed for one of the bank1 registers the double-
register compare mode may be enabled for this register (see Section 17.5.5).
For the exact operation of the port output signal, please see Section 17.6.
User’s Manual
CC12_X1, V2.1
17-15
V2.2, 2004-01