XC161 Datasheet, PDF (235/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
20.4
Interrupt Request Operation
The IIC-Bus Module can generate three different interrupt requests, each with its own
request flag. However, due to the nature of these requests, it is sufficient to use only two
interrupt nodes to process the requests. As the data interrupt request IRQD and the end-
of-data-transmission interrupt request IRQE both deal with the end of a transfer of a
block of data, their are combined onto one interrupt request line and node, IIC_DIRQ, as
shown in Figure 20-5.
Interrupt
Request
Circuitry
IRQD
>^_ 1
IRQE
IRQP
IIC_DIRQ
IIC_PEIRQ
MCA05467
Figure 20-5 IIC-Bus Module Interrupt Wiring
The request flags for the three possible interrupt sources are located in the status
register ST. The conditions for the activation of the requests and for handling of the
request flags are detailed below.
As long as one or more of the interrupt request flags are set, and the IIC-Bus Module
operates in Master Mode or has been selected as a slave, the clock line SCL is held at
low level to prevent further transactions on the bus. The clock line is released again when
all three flags are set to 0. Then, further transactions can take place on the IIC bus.
This operation can also be used to control IIC-Bus transactions by setting or clearing the
request flags by software.
Data Transfer Event Interrupt, IRQD
This request is activated and the flag is set when the specified buffer is either empty (in
transmit mode) or full (in receive mode). For example, when the buffer size is set to
3 bytes (via CI) and all three buffer locations, RTB0, RTB1, and RTB2, have been written
with transmit values, then the request will be activated when the last byte in RTB2 has
been sent via the IIC-Bus.
IRQD is also activated in Slave-Transmitter Mode, when a transfer was terminated by
the current master before all data in the slave’s transmit buffer has been sent. This is in
addition to the activation of interrupt request IRQE.
If the automatic interrupt flag clear operation is selected (bit CON.INT = 0), then flag
IRQD is automatically cleared by hardware upon a complete read or write access to the
buffer(s) RTB0 … 3. If CON.INT = 1, then flag IRQD must be cleared by software.
User’s Manual
IIC_X, V2.0
20-17
V2.2, 2004-01