XC161 Datasheet, PDF (408/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Register Set
Table 23-2 LXBUS Register Listing (cont’d)
Short Name
Physical
Address
Description
CAN_BECNTL 20’0260_H Node B Error Counter Register Low
CAN_BECNTH 20’0262_H Node B Error Counter Register High
CAN_RXIPNDL 20’0284_H Receive Interrupt Pending Register Low
CAN_RXIPNDH 20’0286_H Receive Interrupt Pending Register High
CAN_TXIPNDL 20’0288_H Transmit Interrupt Pending Register Low
CAN_TXIPNDH 20’028A_H Transmit Interrupt Pending Register High
Interrupt Control
CAN_0IC
00’F196_H1) TwinCAN Interrupt Control Register 0
CAN_1IC
00’F142_H1) TwinCAN Interrupt Control Register 1
CAN_2IC
00’F144_H1) TwinCAN Interrupt Control Register 2
CAN_3IC
00’F146_H1) TwinCAN Interrupt Control Register 3
CAN_4IC
00’F148_H1) TwinCAN Interrupt Control Register 4
CAN_5IC
00’F14A_H1) TwinCAN Interrupt Control Register 5
CAN_6IC
00’F14C_H1) TwinCAN Interrupt Control Register 6
CAN_7IC
00’F14E_H1) TwinCAN Interrupt Control Register 7
1) This register is located in the ESFR area.
Reset
Value
0000_H
0060_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
The base address of each Message Object n, where n = 0-31, is listed in Table 23-3.
The offset address of each register in Message Object n is given in Table 23-4.
Table 23-3 Base Address of Message Objects
Message Object Number
Base Address
Message Object 0
Message Object 1
Message Object 2
Message Object 3
Message Object 4
Message Object 5
Message Object 6
Message Object 7
Message Object 8
20’0300_H
20’0320_H
20’0340_H
20’0360_H
20’0380_H
20’03A0_H
20’03C0_H
20’03E0_H
20’0400_H
User’s Manual
RegSet_X1, V2.0
23-17
V2.2, 2004-01