XC161 Datasheet, PDF (252/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.1.3.5 Node Interrupt Processing
Each CAN node is equipped with 4 interrupt sources supporting the
• global transmit/receive logic,
• CAN frame counter,
• error reporting system.
TXOK
>^_1
Global
CAN
Transmit
and
Receive
Logic
RXOK
LEC
EWRN
BOFF
CAN
Frame
Counter
CFCOV
SIE
LECIE
TRINP
LECINP
>^_1
EINP
EIE
CFCINP
CFCIE
MCA05475
Figure 21-5 Node Specific Interrupt Control
If enabled by bit SIE = ‘1’ in the ACR/BCR register, the global transmit/receive logic
generates an interrupt request, if the node status register (ASR/BSR) is updated after
finishing a faultless transmission or reception of a message object. The associated
interrupt node pointer is defined by bitfield TRINP in control register AGINP/BGINP.
An error is reported by a last error code interrupt request, if activated by LECIE = ‘1’ in
the ACR/BCR register. The corresponding interrupt node pointer is defined by bitfield
LECINP in control register AGINP/BGINP.
The CAN frame counter creates an interrupt request upon an overflow, when the
AFCR/BFCR control register bit CFCIE is set to ‘1’. Bitfield CFCINP, located also in the
AGINP/BGINP control register, selects the corresponding interrupt node pointer.
The error logic monitors the number of CAN bus errors and sets or resets the error
warning bit EWRN according to the value in the error counters. If bit EIE in control
User’s Manual
TwinCAN_X1, V2.1
21-12
V2.2, 2004-01