XC161 Datasheet, PDF (382/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.6
XC161 Module Implementation Details
This section describes:
• the SDLM module related interfaces such as port connections and interrupt control
• all SDLM module related registers with its addresses and reset values
22.6.1 Interfaces of the SDLM Module
In XC161 the SDLM module is connected to Port pins according to Figure 22-18.
f_SDLM
Address
Decoder
Interrupt
Control
SDLM_I0
SDLM_I1
SDLM
Module
(Kernel)
TxD
RxD
MUX
2
PISEL
P4.4_rx
Port 4
Control
P4.4
P4.6_rx
P4.6
P4.7_tx
P4.7
ALTSEL
P7.6_tx
Port 7
Control
P7.6
P7.7_rx
ALTSEL
P7.7
P9.2_tx
Port 9
Control
P9.2
P9.3_rx
ALTSEL
P9.3
Note :- SDLM_I1 shares an interrupt
node with either SDLM_I0 or CAN7INT.
Figure 22-18 SDLM Module IO Interface
The input receive pins can be selected by bitfield RIS in the SDLM_PISEL register. The
output transmit pins are defined by the corresponding ALTSEL registers of Port 4, Port 7
or Port 9.
User’s Manual
SDLM_X, V2.0
22-51
V2.2, 2004-01