XC161 Datasheet, PDF (232/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
If the device has not been selected, it remains idle in Slave Mode.
If the device has been selected, the read/write bit R/W, which has been received
together with the address information, needs to be checked by software to determine the
further actions. If this bit is 0, the slave remains in receive mode, and can read the
incoming message from the buffer RTB0 … 3.
If bit R/W = 1, the master wants to read from the slave device. For this, the slave needs
to prepare the data to be transferred to the master. The data is written to the buffer
RTB0 … 3. Writing to the buffer automatically sets the transfer mode bit TRX to one
(= transmission).
In both cases, operation can only continue when all interrupt flags, IRQD, IRQE, and
IRQP, are cleared. Otherwise, the device holds the SCL clock line low to prevent further
transactions on the IIC-Bus. In this way, a slave is able to suspend bus activities until it
is ready to proceed.
When a stop condition or a repeated start condition is detected, bit SLA is cleared (it will
be set again if the slave is contacted again at the end of the address phase of the new
transaction).
20.3.4 Transmit/Receive Buffer
The IIC-Bus Module has a transmit/receive buffer which can be set to a depth of one to
four bytes. Access to this buffer is performed via the two registers RTBL and RTBH, each
of these represents two bytes of the buffer. The depth of the buffer is specified via bitfield
CI in register CON (1, 2, 3 or 4 bytes).
For a transmission, the bytes to be transferred are written to the respective buffer bytes,
and then transmission is initiated. The data interrupt IRQD is activated when all bytes of
the specified buffer have been transmitted.
In receive mode, the data interrupt IRQD is activated when all bytes of the specified
buffer have been filled with incoming data.
A byte counter, CO in the status register ST, counts the bytes which have been
transferred from the buffer to the IIC-Bus or vice versa. The contents of this counter is
especially of interest in Slave-Transmitter Mode, if the bus transactions have been
terminated by an external master before all bytes of the buffer have been
transmitted.Software can determine the number of correctly transmitted bytes by reading
bitfield CO.
In receive mode, bitfield CO needs to be read in case the transactions have been
terminated (which activates the Protocol Event interrupt request, IRQP), as it represents
the number of correctly received bytes.
Bitfield CO is always cleared to 0 by the correct number (defined by bitfield CI) of
read/write accesses to the buffer registers.
User’s Manual
IIC_X, V2.0
20-14
V2.2, 2004-01