XC161 Datasheet, PDF (242/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
Clock
f_CAN
Control
Address
Decoder
Interrupt
Control
TwinCAN Module Kernel
CAN
Node A
CAN
Node B
CAN
Message Object Buffer
TwinCAN Control
TxDCA
RxDCA
TxDCB
RxDCB
Port
Control
MCB05471
Figure 21-1 General Block Diagram of the TwinCAN Module
The CAN kernel (Figure 21-2) is split into
• A global control shell, subdivided into the initialization logic, the global control and
status logic and the interrupt request compressor.
– The initialization logic sets up all submodules after power-on or reset. After
finishing the initialization of the node control logic and its associated message
objects, the respective CAN node is synchronized with the connected CAN bus.
– The global control and status logic informs the CPU about pending object transmit
and receive interrupts and about the recent transfer history.
– The interrupt request compressor condenses the interrupt requests from
72 sources, belonging to CAN node A and B, to 8 interrupt nodes.
• A message buffer unit, containing the message buffers, the FIFO buffer
management, the gateway control logic and a message-based interrupt request
generation unit.
– The message buffer unit stores up to 32 message objects of 8 bytes maximum
data length. Each object has an identifier and its own set of control and status bits.
After initialization, the message buffer unit can handle reception and transmission
of data without CPU supervision.
– The FIFO buffer management stores the incoming and outgoing messages in a
circular buffer and determines the next message to be processed by the CAN
controller.
– The gateway control logic transfers a message from CAN node A to CAN node B
or vice versa.
– The interrupt request generation unit indicates message-specifically the reception
or transmission of an object.
User’s Manual
TwinCAN_X1, V2.1
21-2
V2.2, 2004-01