XC161 Datasheet, PDF (358/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Register TxDELAY allows for the compensation of the transceiver delay.
TxDELAY
Transceiver Delay Register
Reset Value: 0014_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
RINV
TD
r
rw
rw
Field
TD
RINV
0
Bits Type Description
[5:0] rw
Transceiver Delay Bits
This bitfield defines the transceiver delay, which is
taken into account by the J1850 bitstream processor.
The value of TD determines the number of module
clock cycles, which are taken into account. The reset
value equals 20 µs @ 1.00 MHz or
19 µs @ 1.05 MHz.
6
rw Invert Receive Input
0 Receive pin polarity is not inverted.
1 Receive pin polarity is inverted.
[15:7] –
Reserved; returns ‘0’ if read; should be written with
‘0’.
User’s Manual
SDLM_X, V2.0
22-27
V2.2, 2004-01