XC161 Datasheet, PDF (108/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
17.1
The CAPCOM Timers
The primary use of the timers T0/T7 and T1/T8 is to provide two independent time bases
for the capture/compare channels of each unit. The maximum resolution is 8 t_CC in
staggered mode, and 1 t_CC in non-staggered mode.
The basic structure of the two timers, illustrated in Figure 17-3, is identical, except for
the input pin (see mark).
f_CC
T6OUF
Prescaler ^fTx
TxM
TxI
MUX
Reload
Reg. TxREL
Count
Timer Tx
TxIRQ
TxIN
Edge
Select
TxI
TxR
to
Capure/Compare
Register Array
TxI
x = 0, 1, 7, 8
MCB05419
Figure 17-3 Block Diagram of a CAPCOM Timer
Note: When an external input signal is connected to the input lines of both T0 and T7,
these timers count the input signal synchronously. Thus, the two timers can be
regarded as one timer whose contents can be compared with 32 compare
registers.
The functions of the CAPCOM timers are controlled via the bit-addressable control
registers T01CON and T78CON. The high-byte of T01CON controls T1, the low-byte of
T01CON controls T0. The high-byte of T78CON controls T8, the low-byte of T78CON
controls T7. The control options are identical for all four timers (except for external input).
In all modes, the timers are always counting upward. The current timer values are
accessible for the CPU in the timer registers Tx, which are non bit-addressable registers.
When the CPU writes to a register Tx in the state immediately before the respective timer
increment or reload is to be performed, the CPU write operation has priority and the
increment or reload is disabled to guarantee correct timer operation.
User’s Manual
CC12_X1, V2.1
17-4
V2.2, 2004-01