XC161 Datasheet, PDF (157/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
enabled but empty, an error interrupt EIR will be generated as well with bit OE set. In this
case, the receive FIFO filling level RXFFL is set to 0000_B.
If the RXFIFO is available but disabled (RXFEN = 0) and the receive operation is enabled
(REN = 1), the asynchronous receive operation is functionally equivalent to the
asynchronous receive operation of the ASC module.
The RXFIFO can be flushed or cleared by setting bit RXFFLU in register RXFCON. After
this RXFIFO flush operation, the RXFIFO is empty and the receive FIFO filling level
RXFFL is set to 0000_B.
The RXFIFO is flushed automatically with a reset operation of the ASC module and if the
RXFIFO becomes disabled (resetting bit RXFEN) after it was previously enabled.
Resetting bit REN without resetting RXFEN does not affect (reset) the RXFIFO state.
This means that the receive operation of the ASC is stopped, in this case, without
changing the content of the RXFIFO. After setting REN again, the RXFIFO with its
content is again available.
Note: After a successful autobaud detection sequence (if implemented), the RXFIFO
should be flushed before data is received.
User’s Manual
ASC_X, V2.0
18-14
V2.2, 2004-01