XC161 Datasheet, PDF (347/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

22.2.7 Flowcharts
22.2.7.1 Overview
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
START
Configure J1850
Loading data into TxBuffer
Data transmission
GLOBCON:=19H
CLKDIV:=84H
BUFFCON:=00
load data in
TxBuffer
set TxRQ
J1850 module is enabled
CLKEN is enabled
DIVIDER 5MHz crystal frequency)
FIFO Mode is disabled
TxCPU will not be incremented,
bytes in buffer have to be addressed.
TxDATA10
TxDATA9
TxDATA8
TxDATA7
TxDATA6
TxDATA5
TxDATA4
TxDATA3
TxDATA2
TxDATA1
TxDATA0
3AH
TxBuffer
30H
Transmit data
done
by HW
After succesful transmission
TxRQ:=0
(Bit 1 BUFFCON)
MSGTRA:=1
(Bit 0 TRANSSTAT)
END
An interrupt will be
generated if the
interrupt enable bit
TRAIE is set.
Figure 22-10 Initialization, Data Setup and Transmission
In order to adapt the timing to the transceiver device, register TxDELAY has to be
configured, too. Furthermore, the desired J1850 receive pin and the transmit pin have to
be selected. The interrupt line SDLM_I1 can be combined either with SDLM_I0 or can
be independent.
User’s Manual
SDLM_X, V2.0
22-16
V2.2, 2004-01