XC161 Datasheet, PDF (345/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
In order to monitor the status of the bus during transmission, the SDLM always reads on
the bus, even while transmitting. As a result, the user can check whether the message
sent is equal to the message on the bus (test for arbitration).
The receive buffer in Block Mode can be accessed via register RxD00 on CPU side as
FIFO base address (relative address 40_H). The elements of the FIFO can always be
accessed via their addresses, too. The first eight bytes are located at the relative
addresses 40_H to 47_H, the second eight bytes at the relative addresses 50_H to 57_H.
Rx circular buffer
1
2
1
2
RxCPU=0
0
3
RxCNT=0
15
4
RxCPU=0
0
3
RxCNT=0
15
4
... ...
...
...
RxBuffer before
Block Data reception
16 bytes received,
RxBuffer full
time
MSGREC
1
2
0
RxCPU=0
15
RxCNT=1
3
4
... ...
interrupt generation after
reception of each byte
1
2
0
RxCNT=5
3
15
4
...
...
Block Mode
receive finished
RxCPU=5
time
Figure 22-9 Data Reception in Block Mode
In Block Mode, the interrupt request flags MSGREC (reception) and MSGTRA
(transmission) are automatically reset by hardware upon a read action from RxD00, or a
write action to TxD0 respectively. RBB (= RBC) is set upon a pointer match after
reception of a byte (receive buffer full) and reset by a read action from this buffer.
MSGLST is set if RBB has been set before and a new data byte is received. MSGLST is
not automatically reset by hardware. All error flags remain pending (once set) and have
to be cleared by software. In case of a detected error during transmission, the transmit
request bit TxRQ is reset by hardware in order to abort the transmission (no automatic
retry).
User’s Manual
SDLM_X, V2.0
22-14
V2.2, 2004-01