XC161 Datasheet, PDF (346/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.2.6 Bus Access in FIFO Mode
In FIFO mode (block mode or normal mode), the FIFOs are byte-oriented. In order to
avoid mismatch in case of word accesses, the LSB of the pointers on CPU side select
which byte of the word is taken into account.
In the 16-bit implementation, the LSB of the CPU pointer (RxCPU or TxCPU,
respectively) determines which byte is taken into account. The receive FIFO only
delivers one data byte (its position in the word is selected by the LSB), the other byte is
0. The pointer is incremented by one after each read access to RxD00. The transmit
buffer only takes over one byte per write access to TxD0, according to the LSB of the
pointer. The other byte is not changed.
If the pointer’s LSB is 0, any access to the corresponding buffer is based on the low byte
(read: higher bytes = 0, low byte = FIFO value, write: only low byte written). If the
pointer’s LSB is 1, any access to the corresponding buffer is based on the high byte
(read: high byte = FIFO value, lowbyte = 0, write: only high byte written). In any case, the
pointer is incremented by 1.
Other accesses than to the receive or transmit buffers are always based on the low byte.
Any word access to the SDLM (if FIFO mode is not selected) effects only the low-byte.
User’s Manual
SDLM_X, V2.0
22-15
V2.2, 2004-01