XC161 Datasheet, PDF (386/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.6.2.2 Port Registers
The interconnections between the SDLM module and the IO lines is controlled in the port
logic of Port 4, Port 7 and Port 9. To configure the TxD output, the respective alternate
select registers must be set accordingly. With this setting, the direction of the pin is also
configured as output. The RxD input is connected via the ‘direct in’ to the module kernel,
and it is selected via the PISEL register. The direction of this pin must be set to input via
the Port Direction Control register DP4 or DP7 or DP9.
ALTSEL0P4
P4 Alternate Select Register 0
15 14 13 12 11 10 9
0
r
8765
P7 P6
rw rw
Reset Value: 0000_H
43210
0
r
Field
ALTSEL0
P4.y
Bit
Type Description
7
rw
P4 Alternate Select Register 0 Bit y
0 associated peripheral output is not
selected as alternate function
1 associated peripheral output is selected as
alternate function
ALTSEL1P4
P4 Alternate Select Register 1
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
P7
0
r
rw
r
Field
ALTSEL1
P4.y
Bit
Type Description
7
rw
P4 Alternate Select Register 1 Bit y
0 associated peripheral output is not
selected as alternate function
1 associated peripheral output is selected as
alternate function
User’s Manual
SDLM_X, V2.0
22-55
V2.2, 2004-01