XC161 Datasheet, PDF (344/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.2.5 Block Mode
In Block Mode, the SDLM supports transfer of frames of unlimited length (application
specific). Block mode is selected by BMEN = 1. In this case, only one receive buffer and
the transmit buffer are available. The swap functionality between the two RxBuffers is no
longer supported.
In Block Mode, the receive and the transmit buffers are built as circular buffers of eight
bytes length (transmit buffer) and 16 bytes length (receive buffer, see figures below).
Access in random mode not being useful (but still supported), FIFO mode is
automatically enabled (not depending on RxINCE/TxINCE). During transmission, a
transmit interrupt can be generated each time TxCPU == TxCNT is detected after
transmission of a byte. During reception, a receive interrupt can be generated if
RxCNT0 != RxCPU0 after reception of a byte.
The counting sequence for the transmit buffer is … 6, 7, 0, 1, 2, … representing a circular
buffer of 8 bytes length. The counting sequence for the receive buffer is … 14, 15, 0, 1,
2, … representing a circular buffer of 16 bytes length.
Tx circular buffer
1
2
0
3
TxCPU=0
TxCNT=0
7
4
6
5
Buffer before
CPU loading
1
2
0
3
TxCNT=0
7
4
Tx initiated by
setting TxRQ
1
2
0
TxCNT=5
3
7
4
byte 4 currently
transmitted
interrupt is
generated when
TxCNT=TxCPU
CPU
6
load
5
TxBuffer
TxCPU=5
Block
Mode
6
5
transmission
TxCPU=5
time
1
2
0
TxCNT=5
3
7
4
6
5
CPU continues
loading TxBuffer
1
0
2
3
7
4
6
5
end of Block Mode
transmission
MSGTRA
1
2
0
3
TxCPU=0
TxCNT=0
7
4
6
5
Buffer after
Block Mode transmission
time
Figure 22-8 Transmit in Block Mode
Note: The SW has to take care that the condition TxCPU == TxCNT after writing a byte
to the transmit buffer in block mode does not become true, otherwise the
transmission will be finished.
User’s Manual
SDLM_X, V2.0
22-13
V2.2, 2004-01