XC161 Datasheet, PDF (290/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
Field
Bits Type Description
LECIE
4
rw Last Error Code Interrupt Enable
A last error code interrupt is generated when an error
code is set in bitfield LEC in the status registers ASR or
BSR.
0 Last error code interrupt is disabled.
1 Last error code interrupt is enabled.
CCE
6
rw Configuration Change Enable
0 Access to bit timing register and modification of
the error counters are disabled.
1 Access to bit timing register and modification of
the error counters are enabled.
CALM
7
rw CAN Analyzer Mode
Bit CALM defines if the message objects of the
corresponding node operate in analyzer mode.
0 The CAN message objects participate in CAN
protocol.
1 CAN Analyzer Mode is selected.
0
1, 5, r
Reserved; returns ‘0’ if read; should be written with ‘0’.
[15:8]
1) After resetting bit INIT by software without being in the bus-off state (e.g. after power-on), a sequence of
11 consecutive recessive bits (11 × ‘1’) on the bus has to be monitored before the module takes part in the
CAN traffic.
During a bus-off recovery procedure, 128 sequences of 11 consecutive recessive bits (11 × ‘1’) have to be
detected. The monitoring of the recessive bit sequences is immediately started by hardware after entering the
bus-off state. The number of already detected 11 × ‘1’ sequences is indicated by the receive error counter.
At the end of the bus-off recovery sequence, bit INIT is tested by hardware. If INIT is still set, the affected CAN
node controller waits until INIT is cleared and 11 consecutive recessive bits (11 × ‘1’) are detected on the CAN
bus, before the node takes part in CAN traffic again. If INIT has been already cleared, the message transfer
between the affected CAN node controller and its associated CAN bus is immediately enabled.
User’s Manual
TwinCAN_X1, V2.1
21-50
V2.2, 2004-01