XC161 Datasheet, PDF (210/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
High-Speed Synchronous Serial Interface (SSC)
data on the receive line sent by the selected slave is avoided when all slaves not
selected for transmission to the master only send ones (1). Because this high level is
not actively driven onto the line, but only held through the pull-up device, the selected
slave can pull this line actively to a low level when transmitting a zero bit. The master
selects the slave device from which it expects data either by separate select lines or
by sending a special command to this slave.
After performing the necessary initialization of the SSC, the serial interfaces can be
enabled. For a master device, the clock line MSCLK will now go to its programmed
polarity. The output data line MTX will go to either 0 or 1 until the first transfer will start.
After a transfer, the data line MTX will always remain at the logic level of the last
transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data
transfer by writing the transmit data into register SSCx_TB. This value is copied into the
shift register (assumed to be empty at this time), and the selected first bit of the transmit
data will be placed onto the transmit line MTSR on the next clock from the baudrate
generator (transmission starts only if bit EN = 1). Depending on the selected clock
phase, a clock pulse will also be generated on the SCLK line. At the same time, with the
opposite clock edge, the master latches and shifts in the data detected at its input line
MRST. This “exchanges” the transmit data with the receive data. Because the clock line
is connected to all slaves, their shift registers will be shifted synchronously with the
master’s shift register, shifting out the data contained in the registers, and shifting in the
data detected at the input line. After the preprogrammed number of clock pulses (via the
data width selection), the data transmitted by the master is contained in all the slaves’
shift registers, while the master’s shift register holds the data of the selected slave. In the
master and all slaves, the contents of the shift register are copied into the receive buffer
SSCx_RB and the receive interrupt line RIRQ is activated.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer
data) at line MRST when the contents of the transmit buffer are copied into the slave’s
shift register. Bit BSY is not set until the first clock edge at SCLK appears. The slave
device will not wait for the next clock from the baudrate generator, as the master does.
The reason for this is that, depending on the selected clock phase, the first clock edge
generated by the master may already be used to clock in the first data bit. Thus, the
slave's first data bit must already be valid at this time.
Note: On the SSC, a transmission and a reception takes place at the same time,
regardless of whether valid data has been transmitted or received.
Note: The initialization of the CLK pin on the master requires some attention in order to
avoid undesired clock transitions, which may disturb the other devices. Before the
clock pin is switched to output via the related direction control register, the clock
output level shall be selected in the control register SSCx_CON and the alternate
output be prepared via the related ALTSEL register, or the output latch must be
loaded with the clock idle level.
User’s Manual
SSC_X, V2.0
19-10
V2.2, 2004-01