XC161 Datasheet, PDF (43/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
External Count Clock Input
The external input signals of the GPT1 block are sampled with the GPT1 basic clock (see
Figure 14-2). To ensure that a signal is recognized correctly, its current level (high or
low) must be held active for at least one complete sampling period, before changing. A
signal transition is recognized if two subsequent samples of the input signal represent
different levels. Therefore, a minimum of two basic clock periods are required for the
sampling of an external input signal. Thus, the maximum frequency of an input signal
must not be higher than half the basic clock.
Table 14-9 summarizes the resulting requirements for external GPT1 input signals.
Table 14-9 GPT1 External Input Signal Limits
System Clock = 10 MHz Input
Max. Input Min. Level ^Frequ.
Frequency Hold Time ^Factor
GPT1 Input
System Clock = 40 MHz
Divider Phase _{Max. Input Min. Level}
BPS1 Duration _{Frequency Hold Time}
1.25 MHz
625.0 kHz
312.5 kHz
156.25 kHz
400 ns
800 ns
1.6 µs
3.2 µs
f_GPT/8 01_B
f_GPT/16 00_B
f_GPT/32 11_B
f_GPT/64 10_B
4 × t_GPT
8 × t_GPT
16 × t_GPT
32 × t_GPT
5.0 MHz
2.5 MHz
1.25 MHz
625.0 kHz
100 ns
200 ns
400 ns
800 ns
These limitations are valid for all external input signals to GPT1, including the external
count signals in counter mode and incremental interface mode, the gate input signals in
gated timer mode, and the external direction signals.
14.1.6 GPT1 Timer Registers
GPT12E_Tx
Timer x Count Register
SFR (FE4x_H/2y_H)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Txvalue
rwh
Table 14-10 GPT1 Timer Register Locations
Timer Register
Physical Address
T3
FE42_H
T2
FE40_H
T4
FE44_H
8-Bit Address
21_H
20_H
22_H
User’s Manual
GPT_X1, V2.0
14-29
V2.2, 2004-01