XC161 Datasheet, PDF (371/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Register TXCPU contains the pointers to the next empty byte in the transmit buffer
(= number of bytes in the transmit buffer).
TXCPU
CPU Transmit Byte Counter Register
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
TxCPU
r
rwh
Field
TxCPU
0
Bits Type Description
[3:0] rwh CPU Transmit Byte Counter
Bitfield TxCPU contains the number of bytes, which
have been written to the transmit buffer by the CPU.
In FIFO mode (TxINCE = ‘1’ or BMEN = ‘1’), TXCPU
is incremented by 1 after each CPU write action to
register TXD0. In random mode only (TxINCE = 0
and BMEN = 0), TxCPU has to be written by software
before setting the transmit request bit (TxRQ) in
order to define the number of bytes to be sent.
TxCPU is reset by resetting bit TxRQ in normal mode
or resetting BMEN.
For more details see TxCNT = pointer for CPU
access to transmit buffer in FIFO mode.
[15:4] –
Reserved; returns ‘0’ if read; should be written with
‘0’.
User’s Manual
SDLM_X, V2.0
22-40
V2.2, 2004-01